This invention relates to a method of manufacturing a split-gate flash memory cell of a nonvolatile semiconductor memory.
As a nonvolatile semiconductor memory, an EPROM (Erasable Programmable Read Only Memory) and a flash memory which are capable of erasing and writing information or data are known. Such a nonvolatile semiconductor memory is manufactured in the following manner. On a silicon substrate, a gate oxide film, a floating gate electrode layer for accumulating electrons, an interelectrode insulation film, and a control gate electrode layer to form a word line for each memory cell are deposited and patterned to form a gate electrode of a layered structure which comprises a floating gate and a control gate stacked thereon. Then, a source and drain diffusion layers and a channel region are formed. Thereafter, a metal wiring pattern leading to each electrode is formed.
In case of the flash memory in which each memory cell has the gate electrode of a layered structure comprising the floating gate and the control gate stacked thereon, there is a problem of overerasure upon erasing the data. Specifically, in order to erase the data in the flash memory, the electrons accumulated in the floating gate are removed simultaneously in several thousands or more memory cells. In this event, the amount of the electrons removed from the floating gate fluctuates among individual memory cells. As a result, a threshold voltage fluctuates among the individual memory cells over a variation range on the order of 1V.
In view of the above, the erasure of the data in the flash memory is generally carried out so that the threshold voltage is low. However, if the threshold voltage fluctuates, a particular memory cell may exhibit a depletion transistor characteristic such that the threshold voltage is not greater than 0V. In presence of the particular memory cell exhibiting such a depletion transistor characteristic, electric current continuously flows through a particular bit line connected to the particular memory cell even if the particular memory cell is not read. This makes it impossible to read the data in other memory cells connected to the particular bit line.
In order to eliminate the above-mentioned disadvantage, proposal is made of a split-gate memory cell having a split-gate structure. The split-gate memory cell is different from a memory cell having a gate electrode of an ordinary layered structure in that only a part of the channel region is covered with the floating gate electrode while the remaining part of the channel region is covered with the control gate electrode. Even if the electrons in the floating gate electrode are excessively removed so that the threshold voltage directly under the floating gate electrode is not higher than 0V, the threshold voltage directly under the control gate electrode is not varied from a predetermined threshold voltage designed by a designer. Therefore, a total characteristic of the split-gate memory cell is not the depletion transistor characteristic.
The split-gate memory cell is disclosed, for example, in Japanese Unexamined Patent Publication (JP-A) No. 293566/1996 related to a semiconductor device, a method of manufacturing the semiconductor device, a split-gate transistor, a method of manufacturing the split-gate transistor, and a nonvolatile semiconductor memory.
Generally, the split-gate memory cell is arranged in a memory cell array having a layout in which word lines and bit lines perpendicularly intersect each other so that a specific memory cell can be selected as desired. In a manufacturing process, aluminum wiring patterns as the bit lines are arranged to perpendicularly intersect control gate electrode polysilicon patterns as the word lines. Therefore, it is necessary to form a contact hole for electrical connection between the source/drain diffusion layer of each memory cell and each aluminum wiring pattern. This means that a memory cell area occupied by the memory cell is increased because an extra area is required for the contact hole. It is therefore difficult to reduce the memory cell area.
In order to avoid the above-mentioned problem, it is proposed to use the source/drain diffusion layer as the bit lines. However, the source/drain diffusion layer required to perpendicularly intersect the control gate electrode polysilicon pattern is generally formed prior to formation of the gate electrode. Therefore, the source/drain diffusion layer is not arranged to be self-aligned with respect to the control gate electrode polysilicon pattern. As a result, the memory cell characteristic widely fluctuates in dependence upon the accuracy in pattern arrangement.